The present invention relates to computer-aided design of integrated circuits, and, more particularly, to the estimation of the voltage drop in a system-on-chip(SoC) design.
The number of transistors used in a circuit is increasing exponentially with the development of improved fabrication techniques. At the same time, there has been a manifold increase in the complexity of the circuits that can be made. In the present state of art, an integrated circuit may have millions of transistors. Such complex circuits require the use of complex design tools to model circuit behavior accurately at the design stage.
An accurate prediction of circuit behavior at the design stage is important for the design and fabrication process to be economically viable. Design tools, popularly known as Electronic Design Automation (EDA) tools, are at present used for circuit designing at all levels—from the conceptualization of the design at a functional level to the layout and routing at the transistor level. These EDA tools are used to minimize the design costs, testing costs, time to market, etc. Further, the use of EDA tools enables a test engineer to test the logical/functional correctness of the layout at the fabrication stage.
A related feature of the circuit-designing process is the reusability of a circuit design or a part of a circuit design. Very often, circuit designers use previously designed and characterized logic blocks that perform a small function. For example, an 8-bit multiplier can be designed and characterized once and used in various circuits later. These logic blocks form libraries, which are a collection of logic blocks that perform different functions. When designing a circuit, a circuit designer may choose several different logic blocks from such libraries, and connect them together to realize a more complex function. The libraries also store various characteristics such as supply voltage, current drain, etc., associated with the logic blocks.
A few problems arise while realizing a larger function with smaller logic blocks from the library. For example, when fabricated, the actual behavior of a circuit may deviate from that predicted by the EDA tools. This is because when characterizing with the EDA tools, it is assumed that each of the gates in the logical blocks is supplied with the full supply voltage—Vdd. This, however, does not hold true in a large circuit, because the voltage is supplied through a large network of wires known as a power grid. There is an inevitable resistive drop in the power grid, known as the voltage drop or IR drop. The voltage drop implies that a voltage smaller than Vdd is available at the gates. The greater the distance of a gate from the voltage supply, the smaller is the supply voltage available at the gate.
To account for the voltage drop in a logic circuit, present generation EDA tools provide methods for the estimation of the maximum current drain at the gate level. These estimates are then used to estimate the voltage drop profile in the logic circuit. However, the current drain at a gate depends on its supply voltage and changes significantly with even small fluctuations in the supply voltage. Changes in the current drain, in turn, affect the voltage drop in the power grid, and hence, the supply voltage available at the gate. Therefore, the current drain and the voltage drop are interdependent, where the determination of one depends on the other, and vice versa.
Existing EDA tools do not consider the interdependence of the current drain and the voltage drop, thereby giving unsatisfactory results. For example, in the case of EDA tools for power estimation, while estimating power requirements with ideal supply voltages, it is assumed that all gates in the logic circuit operate at an ideal voltage. This assumption is, however, not valid in the case of a multi-million transistor SoC design.
In the case of power grid analyzer tools, voltage drop analysis is performed with the current values estimated using power estimation EDA tools. The power grid analyzer tools do not provide accurate results as they ignore the fact that the current consumption profile of the logic circuit changes with the fluctuations in the voltage drop.
In the case of Static Timing Analysis (STA) tools, the possibility of on-chip variation of temperature, voltage and process conditions is ignored. However, for Deep Sub-Micron (DSM) and Ultra Deep Sub-Micron (UDSM) designs, studies have shown that this on-chip variation, if ignored, can cause significant performance losses. This is due to the fact that the voltage drop causes the gates to switch slower than usual, introducing errors in the analysis. To accommodate for voltage variations, some of the present day STA tools allow the user to input a value of the supply voltage for each cell. However, relying on user inputs per cell is time-consuming, tedious, and the accuracy of the analysis depends on the accuracy of the voltage value provided by the user.
In light of the above discussion, there is a need for a tool that performs voltage drop analysis in a logic circuit, taking into consideration the interdependence between the voltage drop and the current drain.